verilog reg assignment

Verilog assign statement

Hardware schematic.

Signals of type wire or a similar wire like data type requires the continuous assignment of a value. For example, consider an electrical wire used to connect pieces on a breadboard. As long as the +5V battery is applied to one end of the wire, the component connected to the other end of the wire will get the required voltage.

In Verilog, this concept is realized by the assign statement where any wire or other similar wire like data-types can be driven continuously with a value. The value can either be a constant or an expression comprising of a group of signals.

Assign Syntax

The assignment syntax starts with the keyword assign followed by the signal name which can be either a single signal or a concatenation of different signal nets. The drive strength and delay are optional and are mostly used for dataflow modeling than synthesizing into real hardware. The expression or signal on the right hand side is evaluated and assigned to the net or expression of nets on the left hand side.

Delay values are useful for specifying delays for gates and are used to model timing behavior in real hardware because the value dictates when the net should be assigned with the evaluated value.

LHS should always be a scalar or vector net or a concatenation of scalar or vector nets and never a scalar or vector register.
RHS can contain scalar or vector registers and function calls.
Whenever any operand on the RHS changes in value, LHS will be updated with the new value.
assign statements are also called continuous assignments and are always active

In the following example, a net called out is driven continuously by an expression of signals. i1 and i2 with the logical AND & form the expression.

If the wires are instead converted into ports and synthesized, we will get an RTL schematic like the one shown below after synthesis.

Continuous assignment statement can be used to represent combinational gates in Verilog.

The module shown below takes two inputs and uses an assign statement to drive the output z using part-select and multiple bit concatenations. Treat each case as the only code in the module, else many assign statements on the same signal will definitely make the output become X.

Assign reg variables

It is illegal to drive or assign reg type variables with an assign statement. This is because a reg variable is capable of storing data and does not require to be driven continuously. reg signals can only be driven in procedural blocks like initial and always .

Implicit Continuous Assignment

When an assign statement is used to assign the given net with some value, it is called explicit assignment. Verilog also allows an assignment to be done when the net is declared and is called implicit assignment.

Combinational Logic Design

Consider the following digital circuit made from combinational gates and the corresponding Verilog code.

Combinational logic requires the inputs to be continuously driven to maintain the output unlike sequential elements like flip flops where the value is captured and stored at the edge of a clock. So an assign statement fits the purpose the well because the output o is updated whenever any of the inputs on the right hand side change.

After design elaboration and synthesis, we do get to see a combinational circuit that would behave the same way as modeled by the assign statement.

See that the signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly o becomes 0 when RHS is false. Output o is X from 0ns to 10ns because inputs are X during the same time.

Click here for a slideshow with simulation example !

Verilog Pro

Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?

The difference between Verilog reg and Verilog wire frequently confuses many programmers just starting with the language (certainly confused me!). As a beginner, I was told to follow these guidelines, which seemed to generally work:

Use Verilog reg for left hand side (LHS) of signals assigned inside in always blocks
Use Verilog wire for LHS of signals assigned outside always blocks

Then when I adopted SystemVerilog for writing RTL designs, I was told everything can now be “type logic”. That again generally worked, but every now and then I would run into a cryptic error message about variables, nets, and assignment.

So I decided to find out exactly how these data types worked to write this article. I dug into the language reference manual, searched for the now-defunct Verilog-2005 standard document, and got into a bit of history lesson. Read on for my discovery of the differences between Verilog reg , Verilog wire , and SystemVerilog logic .

Verilog data types, Verilog reg, Verilog wire

Verilog data types are divided into two main groups: nets and variables. The distinction comes from how they are intended to represent different hardware structures.

A net data type represents a physical connection between structural entities (think a plain wire), such as between gates or between modules. It does not store any value. Its value is derived from what is being driven from its driver(s). Verilog wire is probably the most common net data type, although there are many other net data types such as tri , wand , supply0 .

A variable data type generally represents a piece of storage. It holds a value assigned to it until the next assignment. Verilog reg is probably the most common variable data type. Verilog reg is generally used to model hardware registers (although it can also represent combinatorial logic, like inside an always@(*) block). Other variable data types include integer , time , real , realtime .

Almost all Verilog data types are 4-state, which means they can take on 4 values:

0 represents a logic zero, or a false condition
1 represents a logic one, or a true condition
X represents an unknown logic value
Z represents a high-impedance state

Verilog rule of thumb 1 : use Verilog reg when you want to represent a piece of storage, and use Verilog wire when you want to represent a physical connection.

Assigning values to Verilog reg, Verilog wire

Verilog net data types can only be assigned values by continuous assignments. This means using constructs like continuous assignment statement ( assign statement), or drive it from an output port. A continuous assignment drives a net similar to how a gate drives a net. The expression on the right hand side can be thought of as a combinatorial circuit that drives the net continuously.

Verilog variable data types can only be assigned values using procedural assignments. This means inside an always block, an initial block, a task , a function . The assignment occurs on some kind of trigger (like the posedge of a clock), after which the variable retains its value until the next assignment (at the next trigger). This makes variables ideal for modeling storage elements like flip-flops.

Verilog rule of thmb 2 : drive a Verilog wire with assign statement or port output, and drive a Verilog reg from an always block. If you want to drive a physical connection with combinatorial logic inside an always@(*) block, then you have to declare the physical connection as Verilog reg .

SystemVerilog logic, data types, and data objects

SystemVerilog introduces a new 2-state data type—where only logic 0 and logic 1 are allowed, not X or Z—for testbench modeling. To distinguish the old Verilog 4-state behaviour, a new SystemVerilog logic data type is added to describe a generic 4-state data type.

What used to be data types in Verilog, like wire , reg , wand , are now called data objects in SystemVerilog. Wire , reg , wand (and almost all previous Verilog data types) are 4-state data objects. Bit , byte , shortint , int , longint are the new SystemVerilog 2-state data objects.

There are still the two main groups of data objects: nets and variables. All the Verilog data types (now data objects) that we are familiar with, since they are 4-state, should now properly also contain the SystemVerilog logic keyword.

There is a new way to declare variables, beginning with the keyword var . If the data type (2-state or 4-state) is not specified, then it is implicitly declared as logic . Below are some variable declaration examples. Although some don’t seem to be fully supported by tools.

Don’t worry too much about the var keyword. It was added for language preciseness (it’s what happens as a language evolves and language gurus strive to maintain backward-compatibility), and you’ll likely not see it in an RTL design.

I’m confused… Just tell me how I should use SystemVerilog logic!

After all that technical specification gobbledygook, I have good news if you’re using SystemVerilog for RTL design. For everyday usage in RTL design, you can pretty much forget all of that!

The SystemVerilog logic keyword standalone will declare a variable, but the rules have been rewritten such that you can pretty much use a variable everywhere in RTL design. Hence, you see in my example code from other articles, I use SystemVerilog logic to declare variables and ports.

When you use SystemVerilog logic standalone this way, there is another advantage of improved checking for unintended multiple drivers. Multiple assignments, or mixing continuous and procedural ( always block) assignments, to a SystemVerilog variable is an error, which means you will most likely see a compile time error. Mixing and multiple assignments is allowed for a net. So if you really want a multiply-driven net you will need to declare it a wire .

In Verilog it was legal to have an assignment to a module output port (declared as Verilog wire or Verilog reg ) from outside the module, or to have an assignment inside the module to a net declared as an input port. Both of these are frequently unintended wiring mistakes, causing contention. With SystemVerilog, an output port declared as SystemVerilog logic variable prohibits multiple drivers, and an assignment to an input port declared as SystemVerilog logic variable is also illegal. So if you make this kind of wiring mistake, you will likely again get a compile time error.

SystemVerilog rule of thumb 1 : if using SystemVerilog for RTL design, use SystemVerilog logic to declare:

All point-to-point nets. If you specifically need a multi-driver net, then use one of the traditional net types like wire
All variables (logic driven by always blocks)
All input ports
All output ports

If you follow this rule, you can pretty much forget about the differences between Verilog reg and Verilog wire ! (well, most of the time)

When I first wondered why it was possible to always write RTL using SystemVerilog logic keyword, I never expected it to become a major undertaking that involved reading and interpreting two different specifications, understanding complex language rules, and figuring out their nuances. At least I can say that the recommendations are easy to remember.

I hope this article gives you a good summary of Verilog reg , Verilog wire , SystemVerilog logic , their history, and a useful set of recommendations for RTL coding. I do not claim to be a Verilog or SystemVerilog language expert, so please do correct me if you felt I misinterpreted anything in the specifications.

Synthesizing SystemVerilog : Busting the Myth that SystemVerilog is only for Verification
1800-2012 – IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language
1364-2005 – IEEE Standard for Verilog Hardware Description Language
A lively discussion in Google Groups on SystemVerilog var keyword

Sample Source Code

The accompanying source code for this article is a SystemVerilog design and testbench toy example that demonstrates the difference between using Verilog reg, Verilog wire, and SystemVerilog logic to code design modules. Download the code to see how it works!

[lab_subscriber_download_form download_id=8].

16 thoughts on “Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?”

Good article. However, there is one significant gotcha that users need to be aware of. When converting RTL from wire/reg to logic, if you were using a net declaration assignment for a wire, that will not work with logic! As a variable type, assigning a value to a logic variable as part of the declaration merely initializes it to that value. No continuous assignment is inferred.

This is the only case where logic has not been a drop-in replacement for me in RTL.

Example: wire mysignal0 = A & B; // continuous assignment, AND gate logic mysignal1 = A &B; // not synthesizable, initializes mysignal1 to the value of A & B at time 0 and then makes no further changes to it. logic mysignal2; assign mysignal2 = A & B; // Continuous assignment, AND gate

Thanks for pointing that out Evan! I looked through the assignment section of the LRM and you’re correct. Like you said, the particular form of assignment in the first row of your example code is called net declaration assignment (section 10.3.1 of SV-2012 LRM), and as the name suggests it only works on nets. The second line in your example is a variable declaration assignment (section 10.5), and would only initialize the variable and not continuously drive it. That is indeed a gotcha if one just replaced all instances of wire with logic. Great comment!

Would the rules of Verilog concerning blocking assignments(=) for combinational logic always blocks and non-blocking assignments(<=) for sequential logic always block also apply to SystemVerilog ?

Hi Varun. Yes, the same rules would apply when using SystemVerilog logic. You’ll have to be more careful about which SystemVerilog logic signal is intended to be combinational and which is intended to be sequential, because they will look the same in their declaration.

i have an old power verilog model it. i am re-using it and it is giving issues in compilation

it has a statement as below: bit power_on; assign power_on = vddmp & !gndmp;

now compilation is expecting some parentheses at end of “bit power_on;” statement

can anybody help how to solve this compilation issue thanks

Hi Shaily. Thanks for your comment. Are vddmp and gndmp functional signals? Or are they power supplies?

Thanks for a very nice article.

I have a very basic question about the logic design & Verilog.

As far as I know, it is not recommended to have combinational logic include

memory such as flip-flop and latch because it is combinational!

And that is the reason why inferred flip-flops & latch should be avoided,

which is induced by not including all inputs within sensitivity list in always block, uninitialized output, etc.

My question is if the reg variable inside the always *@ block holds the value until the next assignment, it may induce the flip-flops or latches.

Is it allowed to induce a latch or flip-flop inside the combinational logic with some intentions?

Thanks a lot

Hi Jaehyuk. A always@* block will be sensitive to all input signals to the block (with one exception). Therefore, if you use a reg type inside a always@* block, it will become combinational logic and not infer flip-flop or latches.

The one exception is if the always@* calls a function or task, and that function or task contains signals that are external to the function, task, and always@* block. SystemVerilog always_comb avoids this issue, so if you code in SystemVerilog, you should use always_comb instead of always@*. See my other article on always_comb and always_ff

Helpful article, thank you Jason.

Quote: wire [7:0] my_wire_bus; // implicitly means “wire logic[15:0] my_wire_bus”

Is there a minimal width of 16 bit in SystemVerilog or something?

No there isn’t. That just happens to be the example I came up with.

Nice write-up, thanks Jason! BTW, its a nice blog, please keep it up !

Thank you, Jason, for the article! One issue I see in replacing reg with logic is that it eliminates X from the variable. That way you may miss initialization problem. I think also using UPF will force X on the registers during power-down for verification. I am not sure that with that practice it will be compatible with UPF. What do you think?

Hi Dmitry. Using the logic keyword on its own actually declares a 4-state variable, so X’s can also be represented. There is no problem with representing X’s when using UPF, low power simulation, or x-propagation. I have used logic variables successfully on projects that use all these methodologies.

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Hi Jason, Your articles are really helpful. Can you post something related to UVM?